
This module aims to extend students' knowledge of sequential circuits and to give a comprehensive understanding of the main design methods of finite state machines. The students gain an understanding of designing hazard-free circuits including fault detection and testability analysis and are able to achieve a functioning model and a working PLD or FPGA. The students acquire skills in teamwork, project and time management, are prepared for methodical working and know presentation techniques.
Lectures:
Dr. Gero Frömel
Laboratory:
Dr. Gero Frömel
Certification of credits:
Written examination